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International Journal of Modern Computation, Information and Communication Technology

ISSN 2581-5954

September-October 2020, Vol. 3, Issue 9-10, p. 77-84.​​

Design of ripple carry adder using pseudo-NMOS, dynamic circuits and pass transistor logic
R. Indhumathi*, K. Gavaskar, S. R. Nandhini, J. Raja Nandhini
Department of Electronics and Communication Engineering,Kongu Engineering College, Perundurai, Erode,

Tamil Nadu, India – 638060..
*Corresponding author’s e-mail: indhuma2228@gmail.com

Abstract

The present work is mainly focused on area and power of ripple carry adder by using different types of circuit families like pseudo-NMOS logic, dynamic circuit logic and pass transistor logic are used. The main objective of this paper is to reduce the pull-up network or PMOS transistor counts. Because the flow of mobility of electron in PMOS is low so it takes more time. To reduce the PMOS counts, power consumption for RCA by using this logic. In pseudo-NMOS logic, instead of using every PMOS use only one PMOS that is connected to ground. In dynamic circuit logic, instead of connecting PMOS to ground to give clock signal to PMOS to reduce the static power dissipation. In pass transistor logic it uses only pull-down network that means NMOS logic so half of the transistor gets reduced. Based on these results we know that, which logic is efficient to construct the Ripple Carry Adder by using Tanner tool version 13.

Keywords: Dynamic circuits; Pass transistor; Pseudo NMOS; Ripple carry adder.

References

  1. Sasi G, Athisha G. Performance Comparison for Ripple Carry Adder Using Various Logic Design. International Journal of Innovative Technology and Exploring Engineering 2019;8:372-7.
  2. Efstathiou C, Dimolikas K. Low Power and High Speed Static CMOS Digital Magnitude Comparators. IEEE Transactions and Circuit System 2018:145(6);433-36.
  3. Ashish Kumar Y, Bhavana PS. Low Power High Speed 1-bit Full Adder Circuit design at 45 nm CMOS Technology. International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), Bhopal, 2017, pp. 427-432, doi: 10.1109/RISE.2017.8378203.
  4. Flavio C, Felix B. Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.  IEEE Transactions On Very Large Scale Integration Systems 2017:16(7);722-6.
  5. Vishesh D, Richa V. Design of 10T full adder cell for ultralow-power applications. Ain Shams Engineering Journal 2018:9:2363-72.
  6. Rajib K, Durbadal M. Low Power VLSI Circuit Implementation using Mixed Static CMOS and Domino logic with Delay Elements. IEEE Journal of Solid State Circuits 2016;16(3):15-30.
  7. Lee YT, Park IC. Design of Compact Static CMOS Carry Look-ahead Adder Using Recursive Output Property. Electronics Letters 1993;29:794-6. doi: 10.1049/el:19930531.
  8. Deepa, Sampath Kumar V. Analysis of Low Power 1-bit Adder Cells using different XOR-XNOR gates. IEEE International Conference on Computational Intelligence & Communication Technology, Ghaziabad, 2015, pp. 488-492, doi: 10.1109/CICT.2015.21.
  9. Kumar SS, Rakesh S. A Novel high-speed low power 9T full adder. Materials Today Proceedings 2020:24;1882-9.
  10. Aguirre-Hernandez M. Linares-Aranda. CMOS full-adders for energy-efficient arithmetic applications. IEEE Transaction Very Large Scale Integration System 2011;19(4):718-21.
  11. Yogita H, Akalpita L. Design and Implementation of Ripple Carry Adder using area efficient full adder cell in 180nm CMOS Technology. International Journal of Science, Engineering and Technology Research 2014;3(5):1340-45.
  12. Tari HT, Zarandi AD, Reshadinezhad MR. Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders. Microelectronics Engineering 2019;215:110980.
  13. Gavaskar K, Ragupathy US, Malini V. Proposed Design of 1KB Memory  Array  Structure  for   Cache Memories. Wireless Personal Communications 2019;109:823-47.
  14. Gavaskar K, Ragupathy U S. An efficient design and analysis of low power SRAM memory cell for ULTRA applications by Asian Journal of Research in Social Sciences and Humanities 2017:7(1):962-75.
  15. Gavaskar K, Ragupathy US, Malini V. Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories. Wireless Personal Communications 2019:4;2311-39.