October-November 2019, Vol. 2, Issue 10-11, p. 66-70.
Design of Low Power 180 nm Subthreshold 7T Non-Volatile SRAM
R. Priyadharshini, P. Sathyaraj
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam – 612501. Tamilnadu, India.
*Corresponding author’s e-mail: firstname.lastname@example.org
On-chip cache memories are present in every system on chip devices. These cache memories are made up of static random access memory (SRAM). Low power and High speed are the constraints placed on the SRAM cell design. The increased importance of lowering power in memory design has produced a trend for operating memories at lower supply voltages. The implementation of conventional 6T SRAM memory is scaling to newer technology as it operated in the deep submicrometer region has become difficult due to the compromise between area, power, and performance. To overcome the read-write conflicts 7T cell is proposed. The 7T cell is operated at the 0.4v and can also achieve the low area per bit cell by using 0.18µm Technology. The 7T static random access memory has improved read and write stability and noise margin free read operation also in the sub-threshold region.
Keywords: Cache memory; Low power; Seventransistor (7T); SRAM; Subthreshold; Noise margin.
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