ISSN 2581-5954

International Journal of Modern Computation, Information and Communication Technology

October-November 2019, Vol. 2, Issue 10-11, p. 66-70.​​

Design of Low Power 180 nm Subthreshold 7T Non-Volatile SRAM
R. Priyadharshini, P. Sathyaraj
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam – 612501. Tamilnadu, India.
*Corresponding author’s e-mail:


On-chip cache memories are present in every system on chip devices. These cache memories are made up of static random access memory (SRAM). Low power and High speed are the constraints placed on the SRAM cell design. The increased importance of lowering power in memory design has produced a trend for operating memories at lower supply voltages. The implementation of conventional 6T SRAM memory is scaling to newer technology as it operated in the deep submicrometer region has become difficult due to the compromise between area, power, and performance. To overcome the read-write conflicts 7T cell is proposed. The 7T cell is operated at the 0.4v and can also achieve the low area per bit cell by using 0.18µm Technology. The 7T static random access memory has improved read and write stability and noise margin free read operation also in the sub-threshold region.

Keywords: Cache memory; Low power; Seventransistor (7T); SRAM; Subthreshold; Noise margin.


  1. Kirti G, Neeta P, Shourya G, A 32-nm Subthreshold 7T SRAM Bit Cell with Read Assist, IEEE Transactions 2017;25: 3473-83.
  2. Toh SO, Guo Z, Liu TJK, Nikolic B, Characterization of dynamic SRAM Stability in 45 nm CMOS, IEEE J Solid State circuits 2011;46:2702-12.
  3. Chuang C, Kim JJ, Rao RM, Mukhopadhyay S, SRAM Write –ability improvement with transient negative bit-line voltage, IEEE Transactions Very Large Scale Integration system 2011;19:24-32.
  4. Calhoun BH, Nalam S, 5T SRAM with asymmetric sizing for improved read stability, IEEE J Solid State Circuits 2011;46:2431-42.
  5. Bhavnagarwala EJ, Kosonocky S, Chan Y, Stawiasz K; Srinivasan U, Kowalczyk S, Ziegler M, A sub-600- mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing, IEEE Symposium on VLSI Circuits, 14-16 June 2007, Kyoto, Japan.
  6. Kursun V, Tawfik SA, Low power and robust 7T dual-Vt SRAM circuit, IEEE International Circuits System. 2008;1452-55.
  7. Peng C, Xiao S, Lu W, Zhang J, Wu X, Chen J, Lin Z, Average 7T1R nonvolatile SRAM with R/W Margin Enhanced for Low-power Application, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2017;26: 584-8.
  8. Calhoun BH, Chandrakasan A, Wang A, Modeling and sizing for minimum energy operation in Sub threshold circuits, IEEE J Solid State Circuits 2005;40:1778-86.
  9. Calhoun BH, Chandrakasan A, Static Noise Margin Variation for Sub threshold SRAM in 65-nm CMOS, IEEE J Solid State circuits 2006;41:1673-9.
  10. Edri N, Fraiman S, Fish A, Teman A, Data retention Voltage Detection for Minimizing the Standby Power of SRAM arrays, IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 14-17 Nov. 2012, Eilat, Israel.
  11. Yabuuchi M, Morimoto M, Tsukamoto Y, Tanaka S, Tanaka K, Tanaka M, Nii K, 16 nm FinFET high-k/metal- gate 256-kbit 6T SRAM macros with word line overdriven assist, IEEE International Electron Devices Meeting, 15-17 Dec. 2014, San Francisco, CA, USA.