International Journal of Modern Computation, Information and Communication Technology

ISSN 2581-5954

​​June 2018, Vol. 1, Issue 1, pp. 1-7.

Design of Power-Efficient and Wide-Range Voltage Level Shifter     
S. Ramya*, R. Vishnu Priya
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam-612501. Tamilnadu. India.
*Corresponding author’s e-mail:     


The present work presents a wide-range and low-power voltage level shifter for efficient performance in dual-supply applications. The proposed circuit is made efficient by varying the strength of pull-down and pull-up transistors. The width/length ratio is varied, i.e., width/length (strength) is increased for pull-down transistors and decreased for pull-up transistors. This approach is based on the fact that the strength of the pull-up device is lowered while the pull-down device pulls the output down. At the same time, the pull-down device’s strength is increased by an auxiliary circuit that consumes low power. The proposed circuit is simulated in 0.18µm technology Cadence Virtuoso software. The simulation results show that the proposed circuit can convert extremely low level of input voltage into high output voltage level. That is, it can convert low input voltage VDDL=0.7V to high output voltage VDDH=3V with power dissipation of 1.9314 µW.

Keywords: Voltage Level shifter; Low power; Efficiency; Power dissipation; Voltage range.


  1. Wang A, Chandrakasan AP. A 180-nm subthreshold FFT processor using a minimum energy design methodology. IEEE J Solid-State Circuits. 2005;40:310-19.
  2. Usami K, Igarashi M, Minami F, Ishikawa T, Kanzawa M, Ichida M, Nogami K. Automated low-power technique exploiting multiple supply voltages applied to a media processor.  IEEE J Solid-State Circuits. 1998;33:463-72.
  3. Zhang D, Bhide A, Alvandpour A. A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices. IEEE J Solid-State Circuits. 2012;47:1585-93.
  4. Corsonello P, Perri S, Frustaci F. Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. Proc. IEEE Int. Conf. Comput. Design (ICCD). 2015; 499-504.
  5. Lütkemeier S and Ruckert U. A subthreshold to above-threshold level shifter comprising a Wilson current mirror. IEEE Trans Circuits Syst II: Exp Briefs. 2010;57;721-24.
  6. Luo S.-C., Huang C.-J., and. Chu Y.-H. A wide-range level shifter using a modified Wilson current mirror hybrid buffer. IEEE Trans Circuits Syst I: Reg Papers. 2014;61:1656-65.
  7. Lanuzza M, Corsonello P, and Perri S. Fast and wide range voltage conversion in multisupply voltage designs. IEEE Trans. Very Large Scale Integr Syst. 2015; 23:388-91.
  8. Osaki Y, Hirose T, Kuroki N, Numa M. A low-power level shifter with logic error correction for extremely low-voltage digital CMOS LSIs. IEEE J Solid-State Circuits. 2012;47:1776-83.
  9. Hosseini SR, Saberi M, Lotfi R. A low-power subthreshold to above-threshold voltage level shifter.  IEEE Trans. Circuits Syst II: Exp Briefs. 2014; 61:753-57.
  10. Kwong J, Ramadas YK, Verma N,  Chandrakasan AP. A 65 nm sub-Vt microcontroller with integrated SRAM and switchedcapacitor DC–DC converter. IEEE J Solid-State Circuits. 2009;44:115-26.
  11. Chavan A, Mac Donald E. Ultra low voltage level shifters to interface sub and super threshold reconfigurable logic cells.  Proc IEEE Aerosp Conf. 2008;1-6.
  12. Hasanbegovic A, Aunet S. Low-power subthreshold to above threshold level shifter in 90 nm process. Proc NORCHIP Conf. 2009;1-4.
  13. Wen L, Cheng X, Tian S, Wen H, and Zeng X. Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans Circuits and Syst II: Exp Briefs. 2016;63:346-50.
  14. Maghsoudloo E, Rezaei M, Sawan M, Gosselin B. A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter.  IEEE Trans on Circuits and Syst. I: Reg Papers. 2017;64:1164-72.
  15. Lanuzza M, Crupi F, Rao S, Rose RD, Strangio S, Iannaccone G. An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans Circuits and Syst II: Exp Briefs. 2017;64:61-5.