International Journal of Modern Computation, Information and Communication Technology

ISSN 2581-5954

June 2018, Vol. 1, Issue 1, pp. 8-14.​​

Design and Performance Analysis of Inexact-Speculative Han Carlson Adder      
S. Indhu*, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam-612501. Tamilnadu. India.
*Corresponding author’s e-mail:
indhuselvaraj30@gmail.com      

Abstract

Low power and high speed design is one of the important building blocks in digital circuits. In conventional inexact speculative adder based on Carry look-ahead adder to consume more power issues and longest critical path delay. In this paper, Han Carlson adder based design of the proposed ISA architecture which is fine grain pipelined because to increase the processing speed and reduces the complexity, silicon area and power consumption. Additionally this architecture has been clock gated giving rise to dynamic power reduction opportunity. Functional verification and synthesis of suggested ISA is carried out on 45nm CMOS technology by using Tanner EDA tool.

Keywords: Inexact speculative adder; Han Carlson adder; Pipelining; Clock gated.

References

  1. ​Razavi B. Cognitive Radio Design Challenges and Techniques. IEEE Journal of Solid-State Circuits. 2010;45(8):1542-53.
  2. Kim Y, Zhang Y, Li P. An Energy Efficient Approximate Adder with Carry Skip for Error Resilient Neuromorphic VLSI Systems. IEEE/ACM International Conference. 2013;130-37.
  3. Joshi G P, Nam S Y, Kim S W. Cognitive Radio Wireless Sensor Networks: Applications, Challenges and Research Trends. Sensors. 2013;13(9):11196-228.
  4. Fojtik M. An architecture-independent approach to timing-error detection and correction.  IEEE International of Solid-State Circuits Conference. 2014;488-90.
  5. Cilardo A, De Caro D, Petra N. High Speed Speculative Multipliers Based On     Speculative Carry Tree. IEEE Trans Circuits Syst. 2014;3426-35.    
  6. Camus V. Energy-efficient digital design through inexact and arithmetic circuits. IEEE International Conference. 2015;114.
  7. Lin C, Yang Y M. High Performance Low-Power Carry Speculative Addition with Variable Latency. IEEE Trans Very Large Scale Integration Syst. 2015;1591-603.
  8. Ragavan R. Adaptive overclocking and error correction based on dynamic speculation window. IEEE Computer Society Annual Symposium on VLSI. 2016;325-30.        
  9. Shrestha R. High Speed and Low Power VLSI-Architecture for Inexact Speculative Adder. IEEE Transactions on Circuits and Systems. 2017;56-9.
  10. Indhu S, Sriram A. Design and performance analysis of VLSI Architecture for Inexact Speculative Adder. International Journal of Industrial Engineering. 2017;1(7):208-13.
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