International Journal of Modern Computation, Information and Communication Technology
June 2018, Vol. 1, Issue 1, pp. 8-14.
Design and Performance Analysis of Inexact-Speculative Han Carlson Adder
S. Indhu*, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam-612501. Tamilnadu. India.
*Corresponding author’s e-mail: firstname.lastname@example.org
Low power and high speed design is one of the important building blocks in digital circuits. In conventional inexact speculative adder based on Carry look-ahead adder to consume more power issues and longest critical path delay. In this paper, Han Carlson adder based design of the proposed ISA architecture which is fine grain pipelined because to increase the processing speed and reduces the complexity, silicon area and power consumption. Additionally this architecture has been clock gated giving rise to dynamic power reduction opportunity. Functional verification and synthesis of suggested ISA is carried out on 45nm CMOS technology by using Tanner EDA tool.
Keywords: Inexact speculative adder; Han Carlson adder; Pipelining; Clock gated.
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